Graduate Engineer Trainee – Physical Design

Location: Kolkata, West Bengal, India | Experience: Entry Level (0–3 years)

About the Company

HC Robotics Pvt Ltd is hiring motivated engineering graduates for an onsite opportunity in Kolkata. The company is building its technical capability through engineers who can contribute to structured semiconductor design and implementation work. This role sits within the Physical Design team and provides an entry point into ASIC backend engineering, with exposure to high-performance, low-power, and area-optimized semiconductor product development. The organization values disciplined execution, technical learning, analytical problem-solving, and collaboration across RTL, Static Timing Analysis, Design for Test, and Verification functions. New graduates will work alongside experienced engineers while developing practical proficiency in industry-standard Electronic Design Automation tools and physical implementation methods. The position is designed for candidates who have completed dedicated VLSI Physical Design training and want to translate academic or institute-based learning into measurable design-flow outcomes. By joining HC Robotics Pvt Ltd, candidates can build foundational experience across implementation, timing, congestion, power, area, and physical verification activities while contributing to a team focused on reliable backend design execution.

About the Role

As a Graduate Engineer Trainee – Physical Design, you will develop practical capability across the ASIC backend implementation flow in an onsite Kolkata team. Under experienced guidance, you will work on floorplanning, placement, clock tree synthesis, routing, timing analysis, congestion optimization, power and area improvement, and physical verification. The role combines structured learning with supervised execution using industry-standard EDA tools. You will analyze reports, support timing closure, investigate DRC/LVS issues, and document implementation results. Success means building dependable physical design fundamentals, improving design quality across key PPA metrics, and collaborating effectively with adjacent engineering teams. This opportunity is suited to fresh graduates who have completed dedicated Physical Design training and are ready to begin a career in semiconductor backend engineering.

Key Responsibilities

• Execute assigned stages of the ASIC Physical Design flow, including floorplanning, placement, CTS, routing, and physical verification, under supervision to support clean and measurable implementation results.
• Analyze timing, congestion, power, and area reports, then assist with targeted optimization actions that improve design quality and contribute to timing closure.
• Support DRC and LVS issue investigation by reviewing violations, coordinating corrective actions, and documenting closure status to improve physical design readiness.
• Work with synthesis outputs, standard cell libraries, and industry-standard EDA tools to translate logical design inputs into implementation data and reliable backend results.
• Collaborate with RTL, STA, DFT, and Verification teams to resolve cross-functional issues, align constraints, and connect physical implementation decisions with chip-level outcomes.
• Prepare clear design documentation, progress reports, analysis summaries, and technical observations that enable reviews, knowledge transfer, and disciplined project execution.

Essential Skills & Technologies

• Demonstrated training in digital electronics, CMOS, semiconductor fundamentals, ASIC and Physical Design flows, including floorplanning, placement, CTS, routing, timing closure, and STA concepts.
• Understanding of physical verification concepts, including DRC and LVS, together with foundational knowledge of low-power design and power, performance, and area optimization.
• Exposure to one or more relevant EDA tools, such as Cadence Innovus or Tempus, Synopsys ICC2, PrimeTime, Design Compiler, or Mentor Calibre.
• Ability to interpret implementation and timing reports, investigate technical issues, and apply structured analytical and debugging approaches under engineering supervision.
• Foundational familiarity with standard cell libraries, synthesis outputs, advanced technology-node considerations, and the interactions between logical and physical design stages.
• Clear communication, attention to detail, teamwork, and a demonstrated willingness to learn backend VLSI methods through hands-on technical work.

Additional Plus

• Practical exposure to TCL, Linux, shell scripting, Perl or Python, and Git can accelerate automation, repeatability, environment usage, and collaboration within the Physical Design workflow.
• Knowledge of UPF or CPF, multi-voltage design, MMMC, ECO flow, or scan-chain concepts is useful for understanding implementation complexity and supporting broader low-power and signoff requirements.
• Academic or training projects covering ASIC implementation, congestion analysis, timing closure, DRC/LVS, power optimization, low-power design, or full-chip backend execution are advantageous.

What You'll Bring

• You will bring a relevant B.E., B.Tech, or M.Tech background in Electronics and Communication Engineering, Electrical Engineering, Electronics and Instrumentation, VLSI, Microelectronics, or a related discipline. A completed specialized Physical Design training program is preferred, particularly when it includes practical exposure to the complete ASIC backend flow and industry-standard EDA tools.
• You should demonstrate a strong grasp of digital electronics, CMOS, semiconductor fundamentals, physical implementation stages, timing analysis, physical verification, and low-power concepts. The ability to read reports, isolate root causes, and follow through on corrective actions will help you contribute effectively under supervision.
• We value candidates who learn quickly, communicate clearly, maintain attention to detail, and collaborate constructively with adjacent engineering teams. Familiarity with scripting, Linux, version control, MMMC, ECO, multi-voltage concepts, or scan chains will strengthen your profile.
• A genuine interest in semiconductor backend design and readiness to work on advanced technology nodes are essential.

Why Join Us

• Build a career in ASIC backend design by gaining hands-on exposure to the complete Physical Design flow, from floorplanning through routing, optimization, and physical verification.
• Learn alongside experienced engineers while converting structured VLSI training into practical implementation capability, report-based debugging skills, and stronger timing-closure discipline.
• Contribute to high-performance, low-power, and area-optimized semiconductor development by working across PPA analysis, congestion improvement, timing closure, and design-quality objectives.
• Develop cross-functional engineering experience through collaboration with RTL, STA, DFT, and Verification teams in a focused onsite opportunity based in Kolkata.

What We Offer

• A structured entry point into semiconductor backend engineering, with supervised exposure to floorplanning, placement, CTS, routing, timing, congestion, power, area, and physical verification activities.
• Opportunities to apply VLSI Physical Design training on practical engineering tasks, using relevant EDA tools and report-driven analysis to build job-ready implementation skills.
• Collaborative learning with experienced engineers and adjacent technical teams, helping you understand how backend decisions affect timing, power, area, manufacturability, and overall chip quality.
• A Kolkata-based onsite work environment for motivated graduates who want to grow through disciplined execution, technical feedback, documentation, and continuous learning.